Bipolar-plus-DMOS mixed-typology power output stage
US6222414A · kind A · utility
3Cited by
36References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1994 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Dec 7, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/30051
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output power stage which includes a PNP pull-up transistor and an n-channel FET push-down transistor, driven in phase opposition. This fully complementary stage provides an outstandingly improved power handling capability per semiconductor area occupied, together with a large output voltage swing, but does not require the use of externally connected discrete boot-strap components. The bipolar pull-up transistor can optionally be driven through an FET auxiliary stage, to minimize the power requirements of the preceding signal amplification stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.