Render optimization using page alignment techniques
US6222561A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 17, 1998 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Sep 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To reduce the performance penalty associated with frame buffer memory access times for each page when rendering a primitive having scan lines which cross page boundaries, rendering is constrained to a single page at a time. All pixels mapping to a currently-cached frame buffer page are rendered before loading a different frame buffer page into the cache in order to render other pixels within the primitive. Any pixels within a scan region which map to a different page than the active page are temporarily skipped until all pixels mapping to the current page are completed. Only when no more pixels require rendering within the primitive which map to the currently active frame buffer page is another frame buffer page loaded and all pixels mapping to that page are rendered. In processing a scan region which crosses a page boundary, the next pixel or pixel group to be rendered is examined to determine if it maps to the currently active frame buffer page. If so, it is rendered; if not, however, the position is latched, together with any other necessary state information, and rendering proceeds with the next scan region. Once all pixels for a currently active page are rendered, the latched …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.