Digitally synthesized multiple phase pulse width modulation
US6222745A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1999 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Oct 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/1586
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A DC to DC converter includes multiple stages to share power handling. The stages are connected in parallel paths between the source input and the load output of the power converter. An analog error signal is generated by comparing the load output signal to a reference signal. The error signal is fed to a phase shifting input of a phase lock loop. The phase lock loop is connected to receive a reference clock signal and maintain a relative clock signal shifted in phase from the reference clock signal by an amount depending on the error signal. Digital divider circuits and digital logic circuits are used to produce phase shifted variable pulse width control signals for the stages. The parallel connected power conversion stages equally share the transfer of power from the input source to an output load. A single analog to digital conversion of a single analog error signal to multiple, phase shifted, variable duty cycle clocks is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.