Unified program method and circuitry in flash EEPROM
US6222771A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2000 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Jan 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5624
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A unified program method and circuitry for performing concurrently a programming and verifying operation in an array of Flash EEPROM memory cells is provided. Each of the memory cells includes a floating gate array core transistor. A single bandgap voltage is provided which corresponds to a predetermined amount of drain current at which programming is to be terminated. A program voltage is selectively connected to at least one of the columns of array bit lines containing the array core transistor which is to be programmed. A control gate bias voltage corresponding to a programmable memory state is selectively connected to the gate of the array core transistor. A core cell current flowing through the array core transistor and the predetermined amount of drain current is compared. The program voltage is disconnected so as to terminate automatically programming of the array core transistor when the core cell current falls below the predetermined amount of drain current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.