Data-erasable non-volatile semiconductor memory device
US6222774A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 1999 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Sep 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The non-volatile semiconductor memory device comprises memory cell array having a plurality of memory cells, word lines connected to control gates of the memory cells, bit lines connected to drains of the memory cells, a source line connected in common to sources of the memory cells and connected to a well region where the memory cells are formed, a row decoder consisting of a row main decoder and a row sub-decoder for selecting a word line in the memory cell array, a column gate circuits for selecting a bit line in the memory cell array, a control gate driver for biasing a word line in the memory cell array, and an well driver for biasing semiconductor region in which the memory cell array is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.