Output circuit for alternating multiple bit line per column memory architecture
US6222777A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 9, 1999 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Apr 9, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory has memory cells arranged in rows and columns. The memory cells of each row are coupled to a word line that is separate from word lines connecting to the memory cells of other rows. Each column has mutually exclusive subsets of memory cells. The memory cells are coupled to bit lines. Each bit line is coupled to a selected mutually exclusive subset of memory cells. The memory cells of a selected row output a cell voltage on the coupled bit lines when the coupled word line is asserted. A multiplexor receives the cell voltages on the bit lines. The multiplexor is responsive to column select signals to select one of the columns as a selected column, and outputs a multiplexor voltage corresponding to the cell voltage of the memory cell of the selected row and the selected column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.