Method and system for incrementally compiling instrumentation into a simulation model
US6223142A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 1998 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Nov 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are disclosed that utilize the expressiveness of hardware description languages for incrementally compiling instrumentation logic into a simulation model of a digital circuit design. According to the present invention, a simulation model that includes a design entity file of a digital circuit design is generated. Next, an instrumentation entity file is associated with the design entity file, thereby producing an instrumented design entity file. Finally, and during the process of compiling the simulation model, for the instrumented design entity file: searching for a consistent and previously compiled version of said instrumented design entity file. In response to finding a consistent and previously compiled version, loading the consistent and previously compiled version into the simulation model. In response to finding no consistent and previously compiled version, loading and compiling the instrumented design entity file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.