Macroblock variance estimator for MPEG-2 video encoder
US6223193A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1998 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Nov 12, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A hardware accelerator for a coding system for pictures includes an array of lines and columns of pixels, and calculates the variance of macroblocks of a digitized video image for a real-time coding of the current image together with the preceding and successive images, according to the MPEG-2 video algorithm. The architecture minimizes the silicon area needed for implementing the hardware accelerator for a cost-effective reduction on the CPU of the coding system. The use of a plurality of distinct filter/demultiplexers of known architectures is eliminated by conveying the incoming pixels to the respective input lines of distinct variance calculation paths by the use of a simple counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.