Method and apparatus for implementing non-temporal loads
US6223258A · kind A · utility
57Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1998 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Mar 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is described. The processor includes a decoder to decode instructions and a circuit, in response to a decoded instruction, to detect an incoming load instruction that misses a cache, allocate a buffer to service the incoming load instruction, and issue a bus request to load the data in the buffer without accessing said cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.