Microprocessor with reduced instruction set limiting the address space to upper 2 Mbytes and executing a long type register branch instruction in three intermediate instructions
US6223275A · kind A · utility
6Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1998 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Jun 12, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 32-bit RISC processor is disclosed. The bit length of the instruction set is fixed to 16 bits. SLIL and SLIH instructions that cause the address space of 4 Gbytes to be limited to upper 2 Mbytes and that execute a long type register branch instruction are provided. Thus, a register branch instruction can be executed with three instructions rather than five instructions unlike with a related art reference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.