Method and apparatus for ECC logic test
US6223309A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1998 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Oct 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An ECC verification circuit including a first biasing circuit that is configured to output a predetermined logical signal. The verification circuit further includes a switch connected between the first biasing circuit and a first data bit line of a memory data bus of a computer system. The memory data bus includes a plurality of data bit lines and a plurality of check bit lines and the computer system includes error correction circuitry that is coupled to the memory data bus. The verification circuit is configured to activate the switch during a verification cycle of the computer system. In this manner, the predetermined logical signal is applied to the first data bit line during the verification cycle. The verification circuit is designed to apply a test state to the data bit lines and check bits lines of the memory data bus. The test state applied to the check bits line varies from the check bit state that would be generated by the ECC unit of the computer system upon receiving the test state that is applied to the data bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.