Peak error detector
US6223325A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 1998 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | May 12, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/20
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data signal peak error detector for monitoring and detecting undesired shifts in the peak levels of a multilevel data signal, such as an MLT3 Ethernet signal. A signal slicing circuit generates two signals: a data peak detection signal identifies occurrences of data signal peaks and is asserted when the input data signal level has transitioned beyond a value which is intermediate to preceding intermediate and peak (e.g., positive or negative) signal levels; and a data peak error signal identifies occurrences of data signal peak errors and is asserted when the input data signal level has transitioned beyond a value which corresponds to a preceding peak signal level. Assertion of the data peak detection signal initiates a count sequence by a counter. The count sequence is decoded to produce one or more signal pulses, each of which is provided at a respective time after assertion of the first data peak signal and identifies a valid state of the data peak error signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.