Method for processing and integrating copper interconnects
US6225226A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1999 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Dec 13, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming copper interconnects, without inducing copper diffusion, by eliminating the copper chemical-mechanical polishing process. A semiconductor structure is provided having a first metal layer thereover. A first inter-metal dielectric layer is formed over the first metal layer and planarized. A first resist layer is formed over the first inter-metal dielectric layer, and the first resist layer and the first inter-metal dielectric layer are patterned to form via openings with the first metal layer forming the bottoms of the via openings. A barrier/seed layer, comprising a barrier layer and an overlying seed layer, is formed on the sidewalls and bottoms of the via openings. A self-align layer, composed of a high-resistivity, inorganic material, is formed over the barrier/seed layer. The self-align layer is patterned to reform the via openings and to form trench openings, exposing the barrier/seed layer on the bottoms and sidewalls of the via openings and on the bottoms of the trench openings. A copper layer is electroplated onto the exposed barrier/seed layer at the bottoms and sidewalls of the via openings and on the bottom of the trenches. The remaining portions of t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.