Integrated circuit packaging structure
US6225691A · kind A · utility
1Cited by
10References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 2, 1999 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Jul 2, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit packaging structure, which can accommodate two or four memory chips in a single package. The feature rests upon a packaging structure that makes independent data buses between two memory chips, while implementing in parallel the address buses and control buses, and finally encapsulates them within one package in the expectation of doubling the memory capacity without increasing the size of the package and the number of pins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.