Circuit for limiting inrush current through a transistor
US6225797A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2000 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Jun 12, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S323/908
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A power transistor switched power supply connecting a power source to a capacitive load, including a circuit and method for limiting the inrush surge current through the power transistor. The control gate of a junction field effect transistor (JFET) is coupled between the conductive path of the power transistor and the load to sense voltage drop across the power transistor. The conductive controlled path of the JFET is connected to control the impedance of the power transistor. The JFET shunts some of the power transistor control terminal current during the on transition allowing the power transistor to only turn partially on for a period of time, thus limiting the current through the power transistor from the power source to the load. Because the inrush surge current is limited, the accompanying transient power source voltage drop is reduced with less impact to other circuits connected to the power source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.