Transmission line impedance matching output buffer
US6225819A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1998 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Mar 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/028
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An output buffer includes a continuously variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such as a pullup/pulldown transistor, for receiving an input signal and generating an output signal on an output node in response thereto. In addition, the buffer includes a control circuit and a low-impedance driver in an electrical communication with the output node and, preferably, disposed in parallel with at least one of the pullup and/or pulldown transistors. The control circuit receives the output node voltage and generates a control signal on a control node that varies according to the magnitude of the output node voltage. The driver is biased by the control signal and has a conductivity that varies according to the control signal. The variations in the conductivity are operative to adjust the output impedance of the buffer. The control circuit may include a voltage follower circuit that maintains an offset between the output node voltage and the control node voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.