Semiconductor memory device with hierarchical control signal lines
US6226208A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 1999 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Dec 6, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Only one sense signal line for driving a sense amplifier is arranged in each sense amplifier band. Each sub-array is provided with a sub-sense signal generator for generating two sub-sense signals in response to a main sense signal sent from one main sense signal line. The sub-sense signal is applied to the plurality of sense amplifiers corresponding to each sub-array. Since only one main sense signal line is arranged in each sense amplifier, a layout area is reduced. Preferably, a transistor of a first inverter in the sub-sense signal generator is smaller in size than a transistor of a final inverter. Thereby, a significant delay of the sub-sense signal does not occur in a position remote from a source of the main sense signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.