Low latency dynamic random access memory
US6226223A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2000 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Feb 23, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory device with multiple memory cells, each including a charge storage device and two transfer devices for transferring its charge, these memory cells are accessible with no select signal provided externally. The memory device includes a clock generator for generating first and second mutually complementary clock signals. In response to the first and second clock signals, one of first word lines and one of second word lines are activated alternately. Specifically, the first clock signal makes a memory cell accessible through a first bit line by activating the first word line and first transistor, while the second clock signal makes the memory cell accessible through a second bit line by activating the second word line and second transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.