Information handling system including non-disruptive command and data movement between storage and one or more auxiliary processors
US6226695A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1995 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Sep 29, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information handling system which efficiently processes auxiliary functions such as graphics processing includes one or more processors, a high speed processor bus connecting the one or more processors, a memory controller for controlling memory and for controlling the auxiliary function processing, a memory system, and an I/O bus having one or more I/O controllers with I/O devices connected thereto. The system further includes means in a processor for building a queue of command blocks related to the auxiliary function processor, writing one or more command blocks to memory, which may include a processor cache, writing a start address for each command block to an address FIFO associated with the auxiliary function processor, reading a command block queue start address by the auxiliary processor, recognizing the command block read, issuing a coherent read for queued command blocks with intervention enabled, flushing a copy of the queued command block from processor cache to memory subsystem if a copy of the queued command block is in processor cache, intercepting the flushed copy of the queued command block from cache to memory and canceling the read to memory, storing the queue…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.