Method and apparatus for reducing the apparent read latency when connecting busses with fixed read replay timeouts to CPU'S with write-back caches
US6226703A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 1998 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Nov 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided for reducing read latency for an I/O device residing on a bus having a short read latency timeout period. The apparatus includes a I/O bridge on an I/O bus having a longer read latency timeout which modifies read transactions into two separate transactions, a write transaction to the same address requested by the read transaction which will force a write-back if the address hits in the CPU's write-back cache, and then performing the read transaction which is performed after a predetermined period of time following initiation of the write transaction. This removes the possibility of a device on the I/O bus having a short read latency timeout period from exceeding it's read latency timeout limit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.