Method and apparatus for generating error detection data for encapsulated frames
US6226771A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1998 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Dec 14, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0041
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An error detection generator calculates error detection data for insertion into encapsulated frames. The error detection generator is configured to calculate multiple error detection values and insert them into corresponding fields of the encapsulated frames. The error detection generator includes a controller, three cyclic redundancy check (CRC) engines and at least one multiplexer. Each CRC engine is selectively enabled by the controller to calculate a frame check sequence (FCS) value on a different portion of the frame. Downstream CRC engines also receive the outputs from the upstream CRC engines so that these earlier FCS values may be used during subsequent calculations. The outputs of the CRC engines are also inserted into the appropriate fields of the encapsulated frames by the multiplexer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.