Microcap wafer-level package with vias
US6228675A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 1999 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Jul 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microcap wafer-level package is provided in which a micro device is connected to bonding pads on a base wafer. A peripheral pad on the base wafer encompasses the bonding pads and the micro device. A cap wafer is processed to form wells of a predetermined depth in the cap wafer. A conductive material is made integral with the walls of the wells in the cap wafer. The cap wafer has contacts and a peripheral gasket formed thereon where the contacts are capable of being aligned with the bonding pads on the base wafer, and the gasket matches the peripheral pad on the base wafer. The cap wafer is then placed over the base wafer so as to bond the contact and gasket to the pads and form a hermetically sealed volume within the peripheral gasket. The cap wafer is thinned to form a "microcap". The microcap is thinned below the predetermined depth until the semiconductor dopant is exposed to become conductive vias through the cap wafer to outside the hermetically sealed volume.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.