Low stress method and apparatus for underfilling flip-chip electronic devices
US6228680A · kind A · utility
22Cited by
6References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 1, 1999 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | May 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor assembly and method of fabrication comprising an integrated circuit chip, an electrically insulating substrate, a multitude of solder balls for interconnecting both parts while spacing them apart by a gap, and a polymeric encapsulant filling the gap. The method of fabrication includes heating and cooling cycles, based on stress modeling, such that all mechanical stress levels in the dielectric layers of the circuit chip and in the solder balls are reduced to levels safe for operating the semiconductor assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.