Silicon-on-insulator devices and method for producing the same
US6228691A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 1999 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Jun 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76272
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process of producing controllable thicknesses of silicon-on-insulator (SOI) for fully-depleted double-gate applications is provided. The process comprises depositing an oxide layer on a silicon wafer, depositing a nitride layer of a controlled thickness on the oxide layer, etching the nitride layer to open a first trench of controlled thickness, opening a second trench down to the silicon substrate, growing epitaxial silicon using epitaxial lateral overgrowth (ELO) to fill the second trench and grow sideways to fill the first trench, perform planarization of ELO silicon using the nitride layer as a chemical-mechanical polishing (CMP) stop layer, and fabricating a SOI device in the first trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.