Method to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate
US6228695A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 1999 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | May 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A split-gate flash memory cell having self-aligned source and floating gate self-aligned to control gate is disclosed as well as a method of forming the same. This is accomplished by depositing over a gate oxide layer on a silicon substrate a poly-1 layer to form a vertical control gate followed by depositing a poly-2 layer to form a spacer floating gate adjacent to the control gate with an intervening intergate oxide layer. The source is self-aligned and the floating gate is also formed to be self-aligned to the control gate, thus making it possible to reduce the cell size. The resulting self-aligned source alleviates punch-through from source to control gate while the self-aligned floating gate with respect to the control gate provides improved programmability. The method also replaces the conventional poly oxidation process thereby yielding improved sharp peak of floating gate for improved erasing and writing of the split-gate flash memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.