Alignment method for semiconductor device
US6228743A · kind A · utility
21Cited by
7References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 1998 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | May 4, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A semiconductor wafer (101) includes a first semiconductor die (103) having a first alignment mark (165) disposed in an alignment region (163) to align the first semiconductor die on the wafer. A second semiconductor die (181) has a second alignment mark (167) disposed in the alignment region such that the second alignment mark overlaps the first alignment mark. The area occupied by the overlapping alignment marks is shared between the first and second semiconductor dice to reduce the area and the cost of each die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.