Semiconductor device, and manufacturing method therefor
US6228755A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 1999 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Mar 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described is a semiconductor device having a buried multilayer wiring structure, in which there is ensured good conductivity among a plurality of wiring layers. A lower wiring pattern is formed from conductive material, and an upper wiring pattern is formed from conductive material. Insulating layers are provided between the lower wiring pattern and the upper wiring pattern. A connection section is formed so as to penetrate through the insulating layers to thereby establish continuity between the lower and upper wiring patterns, as well as to have a greater cross-sectional area at the end facing the upper wiring pattern and a smaller cross-sectional area at the end facing the lower wiring pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.