Process for fabricating semiconductor device without separation between silicide layer and insulating layer
US6228766A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 21, 1998 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Jan 21, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Dopant impurities are ion implanted into active areas assigned to field effect transistors, and, thereafter, titanium silicide layers are formed from a titanium layer on the doped regions; when the dopant impurities are ion implanted into the doped regions, photo resist ion-implantation masks prevent a wide inactive area not assigned to any circuit component from the dopant impurities, and a thick titanium silicide is also grown on the wide inactive area; even when the titanium silicide layers are annealed with heat, the thick titanium silicide layer on the wide inactive area is not seriously coagulated, and an inter-level insulating layer is hardly separated from the titanium silicide layer on the wide inactive area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.