Semiconductor memory device using inverter configuration
US6229186A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 1999 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Apr 29, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device provided with a plurality of memory cells each including first transistors having first conductivity type and second transistors having a second conductivity type, each memory cell comprising a first active region where channels of the first transistors are formed and a second active region where channels of the second transistors are formed, the first and second active regions being arranged so that the directions of channel currents of the transistors become parallel to each other in each cell and being separated between adjoining memory cells in a direction perpendicular to the directions of channel current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.