Voltage regulator compensation circuit and method
US6229292A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2000 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Apr 25, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/565
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method and circuit enable a voltage regulator to employ the smallest possible output capacitor that allows the regulator's output voltage to be maintained within specified boundaries for large bidirectional step changes in load current. This is achieved with a technique referred to as "optimal voltage positioning", which keeps the output voltage within the specified boundaries while employing an output capacitor which has a combination of the largest possible equivalent series resistance (ESR) and lowest possible capacitance that ensures that the peak voltage deviation for a step change in load current is no greater than the maximum allowed. The invention can be used with regulators subject to design requirements that specify a minimum time T.sub.min between load transients, and with those for which no T.sub.min is specified. When no T.sub.min is specified, optimal voltage positioning is achieved by compensating the regulator to ensure a response that is flat after the occurrence of the peak deviation, which enables the output voltage to remain within specified limits regardless of how quickly load transients occur. Another embodiment enables the power consumption of the device b…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.