Phase selection circuit
US6229344A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 9, 1999 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Mar 9, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/131
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Phase selection circuit for selecting a phase from signal source generating a multi-phase clock signal is implemented utilizing a single stage of multiplexing gates for receiving taps from signal source, thus minimizing mismatch between phases. Multiplexing gates, connected together at their outputs, select between a tap and an inverse tap and are always left on. The outputs from multiplexing gates are analog summed together to create a single phase output signal which may be shifted in phase by one tap simply by inverting one of the input taps to a multiplexing gate, thus reducing glitching at output signal. Phase interpolation is provided for by further phase shifting the output in steps smaller than one tap utilizing multiplexor circuit which interpolates in multiple steps between a tap and inverse tap. Phase selection circuit provides for provides maximum bandwidth capability, while minimizing mismatch and glitching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.