Method and apparatus for reducing the disparity of set and clear bits on a serial line
US6229462A · kind A · utility
0Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1999 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Mar 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for minimizing a disparity of set and clear bits transmitted across a serial line is disclosed. The method operates by determining a line disparity by examining n-bit datawords that are transmitted. The method also determines a dataword disparity is determined for a dataword yet to be transmitted. The dataword yet to be transmitted is then inverted before transmission if the line disparity and the dataword disparity have the same sign.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.