Method and apparatus for support of multiple memory devices in a single memory socket architecture
US6229727A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 1998 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Sep 28, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for supporting multiple configurations/sizes of random access memory devices in a single socket architecture is provided. In general, the address lines of the microprocessor are interconnected through a multiplexer and buffer arrangement that divides the address lines into two groups. The two groups of address bits, so divided, are selectively routed to predetermined pin connections of a dual in-line memory module (DIMM) socket that interconnect with predetermined address lines of the resident random access memory. The address bits are transmitted to the pin connections during each of the row address cycle and the column address cycle of the memory. The interconnections between the multiplexer/buffer and the random access memory are arranged so that a variety of standardized address pin configurations are supported by the same socket.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.