Method and apparatus for a phase locked loop
US6229774A · kind A · utility
9Cited by
5References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 21, 1999 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Jan 21, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1403
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A PLL circuit and a phase locking method for rapidly phase locking a sample signal to a target clock. The phase locked loop (PLL) circuit comprises: a voltage controlled oscillator; an error correction logic circuit for determining a phase difference between a signal output by the voltage controlled oscillator and a target signal; and a controllable variable delay circuit for determining a delay of the signal output of the voltage controlled oscillator instantly on the basis of an initial phase difference that is determined by the error correction logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.