Clock distribution network utilizing local deskewing clock generator circuitry
US6229861A · kind A · utility
35Cited by
9References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock signal distribution network for a high-speed microprocessor includes a clock synthesizer coupled to receive an externally generated clock signal. The clock synthesizer deskews the external clock to generate an internal clock signal, which is then distributed about the semiconductor die by a conductivity tree. A set of local deskewing clock generators are coupled to branch interconnects of the tree and function as a zero-delay buffers for driving proximally located circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.