Finite field multiplier with intrinsic modular reduction
US6230179A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Dec 24, 1997 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Dec 24, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/382
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A finite field multiplier with intrinsic modular reduction includes an interface unit (1208) that translates an n bit wide data path to a m bit wide data path where n is less than m. Also included is a finite field data unit (1204) with m bit wide registers that is coupled to a finte field control unit (1202). The finite field control unit (1202) includes a microsequencer (1402) and a finite state machine multiplier (1404). The microsequencer (1402) controls the finite state machine multiplier (1404) which performs a finite field multiply operation with intrinsic modular reduction and presents a finite field multiplication product to the finite field data unit (1204).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.