Semiconductor device and manufacturing method thereof
US6232209A · kind A · utility
34Cited by
3References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1999 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Nov 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/664
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate electrode includes a polycrystalline silicon layer, a barrier layer and a metal layer. The metal layer and barrier layer includes for example W and RuO.sub.2 layers, respectively. In forming the gate electrode, the metal layer and barrier layer are etched using at least one of the barrier layer and polycrystalline silicon layer as an etching stopper.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.