Bipolar silicon-on-insulator structure and process
US6232649A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 12, 1994 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Dec 12, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
Abstract
A process for fabricating a bipolar transistor on a silicon-on-insulator substrate which includes etching a bipolar transistor area into the substrate, wherein the bipolar transistor area has substantially vertical sidewalls and a bottom, and forming a buried collector in bottom of the bipolar transistor area. Polysilicon sidewalls are formed adjacent to the vertical sidewalls in the bipolar transistor area, wherein the polysilicon sidewalls are connected to the buried collector. The polysilicon sidewalls are oxidized to form a layer of oxidized polysilicon. Oxide sidewalls are formed on the oxidized polysilicon sidewalls, and epitaxial silicon is formed to fill the bipolar transistor area. A base and an emitter are formed for the bipolar transistor, within the epitaxial barrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.