Low noise low distortion class D amplifier
US6232833A · kind A · utility
23Cited by
4References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 10, 1999 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Nov 10, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/372
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The low jitter dead time circuit which uses one RC combination to set the turn on delay for both the upper and lower MOSFETs in the half bridge. This circuit minimized jitters in the turn on delay and results in matched turn on delays for both MOSFETs in a half bridge. This minimizes noise and distortion. This circuit is further designed to be used in conjunction with shunt regulators to reject ripple from the power supplies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.