Clocking technique for reducing sampling noise in an analog-to-digital converter
US6232905A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 1999 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Mar 8, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are disclosed for improving the operation of an analog-to-digital converter ("ADC"). A separate "clean" oscillator clock is to be used in combination with a "noisy" ADC clock being regulated by a phase-locked-loop (PLL) circuit. The "noisy" ADC clock drives the digital control logic and also turns on the sample signal for the purpose of sampling. The second clock, which has a substantially fixed (i.e., "clean") frequency is used to generate a short pulse, the leading edge of which turns off the sample signal, thereby providing an improved sampling process with greater resolution. The interaction of the two clocks is controlled with digital logic circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.