Parasitic capacitance reduction for passive charge read-out
US6233012A · kind A · utility
8Cited by
9References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 5, 1997 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Nov 5, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit technique to reduce the input capacitance line of a charge integrator is described. This approach is particularly tailored for embedded read-out circuits in solid-state integrated sensors. An integrated charge amplifier described herein includes a generic amplifier element and a high speed buffer which drives a metal shield placed underneath the input line. The metal shield therefore follows the potential of the input line and thereby reduces the capacitance between the input line and ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.