Sense amplifier circuit, memory device using the circuit and method for reading the memory device
US6233170A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 16, 1999 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Dec 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The bit lines BL1 and BL2 is precharged to a potential VCC/2, and the plate line PL1 is set to a potential VCC/2. All word lines WL1 and WL2 are set to the high potential so as to sustain the connection node of one terminal of the ferroelectric capacitance and source terminals of cell transistors TC11 and TC12 to a potential VCC/2. After that, all lines except the word line WL1 to be selected are set to the ground potential. The sense amplifier enable signal SAN is set to the ground potential so as to make NMOS transistors MN1 and MN2 in conduction. The charge in a bit line capacitance and a ferroelectric capacitance is discharged to the ground potential. In this case, a signal voltage that can be detected by the sense amplifier SA is generated on the two bit lines BL1 and BL2, so the signal voltage can be amplified by turning on PMOS transistors MP1 and MP2. Thus, a ferroelectric memory device is provided that can realize reading and writing operation by a simple control so as to improve substantially the operation speed and the power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.