Non volatile semiconductor, memory
US6233174A · kind A · utility
9Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2000 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Mar 30, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device having a plurality of memory cells. Each cell stores data and has a threshold voltage corresponding to the data. A controller controls a partial erase operation in response to a command. This operation includes selecting memory cells in two groups, storing the data in a data latch, writing erase data indicating an erase state, erasing data of selected cells and programming the data stored in the data latch to selected memory cells and programming the erased data to selected memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.