Semiconductor integrated circuit and method for testing memory
US6233182A · kind A · utility
40Cited by
4References
37Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1999 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Dec 15, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a predetermined algorithm and reading written data, an arithmetic unit, and data determining means for determining the read data and outputting the result of determination is provided over a semiconductor chip equipped with a memory
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.