Apparatus and method for retrofitting multi-threaded operations on a computer by partitioning and overlapping registers
US6233599A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 1997 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Jul 10, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for performing multithreaded operations includes partitioning the general purpose and/or floating point processor registers into register subsets, including overlapping register subsets, allocating the register subsets to the threads, and managing the register subsets during thread switching. Register overwrite buffers preserve thread resources in overlapping registers during the thread switching process. Thread resources are loaded into the corresponding register subsets or, when overlapping register subsets are employed, into either the corresponding register subset or the corresponding register overwrite buffer. A thread status register is utilized by a thread controller to keep track of READY/NOT-READY threads, the active thread, and whether single-thread or multithread operations are permitted. Furthermore, the registers in the register subsets include a thread identifier field to identify the corresponding thread. Register masks may also be used to identify which registers belong to the various register subsets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.