Apparatus including a host processor and communications adapters interconnected with a bus
US6233643A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1999 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Jun 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pair of communications adapters each include a number of digital signal processors and network interface circuits for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor. Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.