Using FET switches for large memory arrays
US6233650A · kind A · utility
170Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1998 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Apr 1, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a method and apparatus for interfacing a memory array to a memory controller using a field-effect transistor (FET) switch. The memory controller has a bus which comprises a plurality of signal lines. The memory array is coupled to the memory controller. The memory array is divided into N groups of memory devices; each group has K memory devices. K memory devices in each of the N groups share memory signal lines. The FET switch couples the bus to one of the N groups of the shared memory signal lines at different times in response to a switch control indication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.