Method and apparatus for a high-performance embedded memory management unit
US6233667A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1999 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Mar 5, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method and an apparatus for translating a virtual address to a physical address in a computer system. The system receives a virtual address during an execution or a fetch of a program instruction. The system determines if the virtual address is in an upper portion or a lower portion of a virtual address space. If the virtual address is in the lower portion of the virtual address space, the system adds the virtual address to a first base address to produce the physical address. The system also compares the virtual address against an upper bound. If the virtual address has a larger value than the upper bound, the system indicates an illegal access. If the virtual address is in the upper portion of the virtual address space, the system adds the virtual address to a second base address to produce the physical address. The system also compares the virtual address against a lower bound. If the virtual address has a lower value than the lower bound, the system indicates that the access is illegal. Thus, the system provides protection from illegal memory accesses. According to one aspect of the present invention, the system determines if the virtual address…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.