Synchronization device for synchronous dynamic random-access memory
US6233694A · kind A · utility
2Cited by
5References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 14, 1998 |
| Grant date | May 15, 2001 |
| Priority date | — |
| Expiry date | Dec 14, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The device is connected to a memory (7) by an address bus and a data bus. It is characterized in that, on a clock output, it delivers a clock signal (clki_b) to be sent to the clock input of the memory (6), in that the clock signal. (clki) utilized for buffering the addresses and the data to be sent to the memory is the same, with the possible exception of having undergone signal inversion, as the one (clki_b) delivered on the clock output, and in that the same signal (clki_b) is utilized by the buffer (r1) receiving the data from the memory to buffer the data sent by the dynamic memory on the data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.