Wiring structure with divided wiring conductors to achieve planarity in an overlying SOG layer
US6236106A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 26, 1997 |
| Grant date | May 22, 2001 |
| Priority date | — |
| Expiry date | Nov 26, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wiring structure for a semiconductor device comprises a first interlayer insulating film formed on a semiconductor substrate, first level wiring conductors formed on the first interlayer insulating film, a second interlayer insulating film formed to cover the first level wiring conductors and including a SOG film, and a second level wiring conductors formed on the second interlayer insulating film. A first level wiring conductor which is formed in a peripheral zone of a semiconductor chip and which has to have a wide line width, is divided into a plurality of divided wiring conductors having a narrow line width. Alternatively, the first interlayer insulating film in the peripheral zone of the semiconductor chip is etched by a predetermined thickness so that the first level wiring conductor located in the peripheral zone of the semiconductor chip is formed at a level lower than the first interlayer insulating film located in an inside of the semiconductor chip. Therefore, the first level wiring conductor located in the peripheral zone of the semiconductor chip is constituted of a set of the divided wiring conductors having the narrow line width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.